Special purpose computer for determining cut length of elongated material



May 9, 1967 J. s. PAvLENKo ETAL 3,319,055

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May 9, 1967 J. s. PAvLl-:NKO ETAL. 3,319,055

SPECIAL PURPOSE COMPUTER FOR DETERMINING CUT LENGTH OF' ELONGATED MATERIAL Filed DGO. 30, 1955 5 SheetS-Sheet 5 GATE 35 Roor Moron PICKUP vy noor FAcroR sELEcTL'Nc mruLsE 52 couNER l REMNANI/ 6m Y 54 GATE .f

coPY 1 DELAY Lmf OUTLET ggoa 'Fgon 9 WE REGISTER m 6 PLcLLuP PLcLLuP f UNT'MPU 5f V v TMNSFER 50 -RoorrAcroRsELEcLNcmPuLsE COUNTER 44 miem-:uca cmculr Lasciami@ 73 DELAYLLNE l COUNTER GATE V FI y 3 UNITT'RWSLF 57mmfAcToRsELEcrmcmPuLsE man LEVEL ouPuL a SIGNM 8? ALL cAscAoE clncuns (aL-sn L 'm' United States Patent O 3,319,055 SPECIAL PURPOSE COMPUTER FOR DE- TERMINING CUT LENGTH OF ELON- GATED MATERIAL Jury Stepanovich Pavlenko, Izjaslav Vasiljevich Vasiljev,

Victor Grigorjevich Pribysh, Iosif Vladimirovich Sigalov, Petr Timofeevieh Starostin, Nicolai Andronnikovich Tantsjura, Irma Abramovna Fridman, and Victor Evgenjzens Khodosko, all of Kiev, U.S.S.R., assignors to Kievsky Gosudarstvenny Universitat LG. Shevchenko Filed Dec. 30, 1963, Ser. No. 338,553 3 Claims. (Cl. 23S-157) This invention relates to computing machines or rather to devices used to find the most favorable variant for dividing a roll of fabric of arbitrary length into cuts of prerated lengths, which would leave a minimum remnant, when figuring fabrics in needlework factories before laying out the material for cutting.

The eicient utilization of fabrics in needlework factories engaged in mass production of wearing apparel has great economic significance, By reducing the amount of irrational remnants, which cannot be used for turning out articles, the additional amount `of useful articles produced by the industry becomes increased.

The cutting of fabric for mass sewing is done as follows: A r-oll of fabric is cut up into strips, the length of which is sufficient for making one or several articles. Scores of such strips of equal length are subsequently placed into a strip bed one on top of the other and the required articles are cut out simultaneously.

A roll of fabric may be cut into strips of equal length only if the length of the strip is a multiple of the length of the entire roll. However, due to the fact that the length of a fabric roll may be of any size reaching up to `a 100 and more meters, while the length ofV a strip required for a certain article is invariable and runs in the range of l to 12 meters, cases of multiplicity are comparatively rare.

For the purpose of reducing the amount of remnants, estimation is made on the basis of the length of cutting beds for all articles made from the same kind of fabric. If one of the strip lengths is not a multiple of the length of the fabric roll, combinations are made up of two or three strips. Combinations of four strips are seldom practiced in factories for reasons of organizational diiiiculties.

Combinations `are selected with a view of obtaining the least possible remnants. When one or several combinations leave a similar amount of remnants, preference is given to the combination, which contains the smaller number of strips of equal length. Under equal conditions the problem is decided on the basis most favorable to the assortment of products.

Finding Iof the most favorable combination comes down to solving a system of diophantine equations, such as:

A:the length 4of the roll of fabric expressed in cm.

a=the length of the strip bed expressed in cm.

i, k, l=the numbers of strips acquiring all kinds of values from 1 to z' in accordance with the inequality of i k l :the largest number of strips.

mi, n, p:the quantity of strips of equal length.

=the remnant ICC and then to the selecting Aof the most favorable solution ensuring the smallest (remnant).

The number of equations equals the number of combinations of i multiplied by 3. In order to explain the equations given, the sequence of compiling the equations and their solution should be considered in more detail, as follows:

For purposes of selecting the optimum variant of cut ting up a roll of fabric it is necessary to compile all the equations and to find all the solutions for each of them, then select the best one.

If the cutting is to be performed for three strip beds, then it is described by one equation If, however, the calculation of how to cut a piece of fabric is to be carried out on the basis of four strip beds, `actually cutting for not more than three strip beds, then four equations can be compiled, namely,

It is quite obvious that the number of equations rapidly grows with an increase in the number of strip beds for which the calculations are being made.

Each of the equations given above contains four unknowns, namely, m, n, p and o, as a result of which there may exist a large number of alternative solutions, which can be found by the method of trial computations.

The vabove is illustrated with an example, wherein for purposes of clarity simple values will be used, viz., A=60, 11:10, a2: 12, :13:15.

The last equation set forth above can have a multitude of solutions for these values, some of which are given below:

111:6, 1t:p:o:0

m:3, 11:0, p:2, 0:0 111:2, 11:2, p:l, 0:1 171:1, 11:4, p:1, 0:2

('7) 111:3, 7Z:1, 17:1, 0:3, etc.

For selecting the optimum solution, all of the multitude of solutions must be found, and only after this has been done can the optimum one be selected. The roots of the equation, according to the terms of physics, may lbe expressed only by positive integers.

In order to define the most favorable combination, it is necessary to make a great number of computations, which it is not economically expedient to Aaccomplish with the help of ordinary computing machines. Factory calculaftors usually go through selecting various combinations, relying on their intuition and memory at a small number of counting errors. Needless to say, the combinations selected by them -are not Valways the most favorable.

Though eiforts have been made to overcome the above mentioned diiiiculties and shortcomings, no results have been attained, while we have succeeded in solving the problem and in bringing it to a practical realization.

It has now been established that the herein claimed machine possesses rapid action ability, ensuring the finding of the most favorable variant for cutting up a roll of fabric within just a few seconds.

Snly one machine installed at a large needlework fac- `y can fully satisfy the needs of calculating the cuts.

The purpose of this invention is to create a computing tchine capable of finding the most favorable variant cutting up a roll of fabric into strips of prerated length.

Another purpose of this invention is to increase the erating efficiency of computers and designers (planrs).

This invention also ensures the best method of utilizing a fabric by reducing the amount of remnants left over. In connecti-on with the above mentioned purposes this Jention is based on a new construction and combining units and elements herein described and claimed for ,tenting Other advantages of this invention will be sclosed in the description with references to the apnded drawings, in which:

FIG. l shows the functional diagram of the claimed :ctronic computing machine.

FIG. 2 shows the diagram for selecting the factor roots. FIG. 3 shows the diagram of composing diophantine (nations.

FIG. 4 shows the diagram of entering the numbers of ctors.

FIG. 5 shows the diagram of defining the zero remnant :lue on the summation device (summator).

The described electronic computing machine (see FIG. c-onsists of an input device 1, registers 2 for storage the initial data (A and a1 a1), the summator 3, circuits r defining the zero value of the summator remnant, a rogrammer consisting of a block 6 of combinations and counter 7 recording the remnant value, a printing (outut) device 9 and a control device 10.

The automatic fulfilling of the program put into the rachine is ensured by the blo-ck of combinations, con- :cutively forming all the combinations from the lengths f strips and substituting into each equation any possible umber of strips. For this purpose the combination lock contains a circuit for selecting the roots of factors,

circuit for composing the diophantine equations along aree stages of solving these equations, and a circuit for itroducing the factor roots into thewsummator. The ounter for registering the remnant valuesfgthe content of which upon completing the three stages of solving equaions should be increased by one length unit beginning fter the zero value, this counter being engaged parallel o the registers of initial data and connected to the sumnator through the circuit defining the zero value of the actor roots. The summator is connected to the control levice through the circuit for defining the zero value of ts remnant.

The machine operates in the following way:

On the keyboard of the input device type consecutively he values a1, a2 ai (the length of strips) and value i. (the length of the roll of fabric). Through the pushauttons of the register numbers these values are transnitted to the corresponding registers and stored there. 3y pressing the button 11 start on the control device, he synchronizing pulses begin to develop.

By additional code value A is transmitted on the first mpulse from the corresponding register to the summator i (FIG. 1). The value of the remnant is transmitted tfter that by direct code. Also by direct code after that ollows one or the other equation factor transmitted a iefinite number of times. The order observed here is is follows: first transmitted to the summator p num- Jer of times comes the third factor, then n times the iecond factor and after that m times the first factor up :o the moment when the summator shows either zero (which means the end of the solution), or up to the noment of overfilling the summator, when no solution is abtained. In the latter case the signal E is received showing overfilling of the summator.

After obtaining the 4signal 2 the summator is emptied out and the values A are again transmitted into it, as well as value and new combination factors.

TheI cycles of solutions differ as to the value transmitted to the summator (in the first -cycle 6:0, in the second cycle 5:1 and so on).

The solution stages differ from each other by the quantity of various factors transmitted to the summator (in the first stage the factor roots of the third p and the second n equal zero; in the second one*p equals 0, in the third-combinations of all three factors are transmitted to the summator.

The selection of factor roots at every stage is accomplished by increasing the values from l to m, p or n.

The chart of selecting factor roots (FIG. 2) contains: counters 12, 13 and 14 for counting the numbers of factor roots m, n and pV respectively; counters 15 and 16 fixing the already used combinations of factor roots and eliminating their further appearance; registers 17 and 18 connected with the outputs of counters 13 and 14 and marking the transition to the next factor root during the process of finding the solution; registers 19 and 20 for recording into the summator the value A--the length 0f the fabric roll-by reverse code and the rated value of the remnant; circuits of coincidence 21, 22 and 23 controlled by the registers 17 and 18 engaged separately and reswitching the chain of registering the factor roots; coincidence circuits 24, 2S and 26 tied up with the circuits for composing equations and the circuit of registration, which separately engage the chains of rearranging the equations in accordance with the solution stages.

The gates 27 and 2S serve for copying by reverse code the readings on the counters 15 and 16 and transferring them to the counters 12, 13 and 14, the gates operating simultaneously at the moment of transition to a new combination of roots.

The first synchronizing pulse passes through the open gate 29, registers the value A from the respective register to the summator and transfers the register 19 into a unit condition. The second synchronizing pulse passes through the `gates 30 and 31, records the Value from the counter to the summator and changes the register 20 into a unit condition. The gate 31 closes and prepares for opening up the coincidence circuits 21, 22 and 23. The selection of one of these circuits is accomplished through the registers 17 and 18, which in this case open up the circuit 21.

This circuit in its turn opens up the gate 32. The following synchronizing pulses pass through the gates 32 and 33 onto the counter 12 counting their number, and at the same time pass on to the recording circuits (output 34), where they record the first factor on the summator. The gate 33 is open constantly and closes only at the signal E showing an ove-rfilled summator.

At the first stage there is a constantly infiowing level s-ignal (input 35), preparing the opening of coincidence circuit 24.

If no solution is obtained, the summator issues Aa signal of overfilling and the coincidence circuit 24 opens up. To make rearrangement of the equation, the next in turn synchronizing pulse passes through the opened up coincidence circuit 24 for composing equations onto the counter 36 of the first factor number and changes its value. Consequently, the next factor will now take its place in the equation. Before starting the next selection, the counters 12, 13 and 14 of the recording numbers and the registers 17 and 1S will return to zero condition. Then the value A is again entered into the summator followed by the value and the next factor.

Every time, when the signal of ove-rfilled summator -is received, the synchronizing pulse retained by the delay line 37, accomplishes through the coincidence circuit 38 a transcription by the reverse recording code of counters 15 and 16 of the used up combination fixations to the corresponding counters 12, 13 and 14 for recording numbers.

At the second stage, when the signal indicating an overfilled summator is received together with the second stage signal (input 39) the register 17 is through the coincidence circuit 40 transferred into a unit condition. Therefore, after recording in the summator the values A and the coincidence circuit 22 will open up first, its outlet pulse opening up the gate 41.

The next in order synchronizing pulse will pass through the gates 41 and 42 to the recording circuit (output 43), where the second factor will be recorded from the respective register to the summator and simultaneously to the counter 13 counting the number of recordings.

Insofar as the counter 13 showed a recording of zero in reverse code, the first pulse will cause its overiilling. This overlling pulse proceeds to the register 17 and transfers it into zero condition; simultaneously it passes on to the counter 15, where it fixes a unit. The register 17 closes the coincidence circuit 22 and opens up the coincidence circuit 21.

The following synchronizing pulses will pass through the gate 32 to the recording circuit (output 34), where the first factor will be recorded on the summator and also the counter 12 counting the number of these recordings.

If no solution has been obtained, which will be signified by the sign of an overtilled summator, the register 17 is again transferred into a zero condition, a unit in reverse code being transcribed from counter to the counter 13. After recording the values A and on the summator, the coincidence circuit 22 opens up. Two pulses for recordingA the second factor will now be required before the counter 13 becomes overlled. The -root combination will now be diiferent. The pulse from the outlet of counter 13 will change the register 17 into initial condition and will add one unit to the counter 15. Recording of the lirst factor takes place in the usual Way. Consequently, the contents of counter 15 become constantly increased. In the future there may be a situation, at which the overiilling of the summator will be reached even before reswitching the register 17, i.e. as soon as the second factor is recorded. In this case the signal indicating overlling lof the summator will open up the coincidence circuit 25, which is prepared for opening by the constantly incoming second stage signal (input 39) from the equation cornposing circuit. The synchronizing pulse Will pass through the circuit 25 into the equation circuit on counter 44, incre-asing by one unit the ordinal number of the second factor. The counters of the root pick-up circuits will in this case return to the initial zero condition, the picking of roots proceeding in the usual way.

On the third stage l(input at 45), when signals indicating an overlled summator -a-re received and of the third stage (outputs 39', 45'), the output pulses of coincidence circuits 40 and 46 will transfer the registers 17 and 18 into a unit condition. First to open up after recording the values A and in the summator, will be the coincidence circuit 23. This circuit opens up the gate 47 and the next synchronizing pulse passes through the gates 47 and 48 to the recording circuit (output 49), where recording of the third factor will take place. Simultaneously, the pulse will pass on to the counter 14, on which a reverse code zero was already recorded. Therefore, the very first pulse will overfill the counter 14. The signal from the counter output will transfer the register 18 into zero condition, causing the closing of the coincidence circuit 23 and the opening of the coincidence circuit 22.

The next pulse to follow into the summator will be the second one and from there on the work will proceed as in the second stage.

During gradual increasing of the second root, -a situation is arrived at, where the signal of overiilling of the summator will appear at the recording of the second factor, i.e. before transferring the register 18. In this case the overfllling signal will open up the coincidence circuit 5i) :and the synchronizing pulse will pass through it to the counter 16 of used up -combin-ations and will increase `its value by one unit. Now two impulses will already be required before transferring the register 18 after copying the readings from counter 16 to counter 14 in reverse code, i.e. the third factor will already have to be entered twice.

The work of the remaining part of the circuit will proceed in a manner similar to that described above.

The gradual increasing of the content of counter 16 will lead t-o a situation, where the overiilling of the summator will occur as soon as only the third factor is recorded, i.e. before the moment of transferring the register 18. Then the signal of summator overiilling will open up the coincidence circuit 26, this opening being already prepared by the third stage signal constantly incoming from the equation composing circuit (input 45). The next synchronizing pulse will pass through it into the equation composing circuit and on to the counter 51, increasing by -one unit the ordinal number of the third factor. In this case the counter of root pick-up return to their initial zero condition. From here on the picking of roots for the new equation will proceed in the same order, as described above.

The circuit for composing diophantine equations consists of: three counters 36, 44 and 51 fixing the numbers of root factors and are connected in parallel to the root pick-up circuit, and four registers 52, 53, 54 and 55, of which two serve to tix the output of the signal of the current stage solution into the circuit of root factor pick-up (to the inputs 35, 39, 45) and the units for the remnant counter (output 56); the other two registers fix the order of root factor selection without repeating the already solved equations and are connected with the outputs of counters 36, 44 and 51, these being interconnected in sequence, in order that the changes in their readings should take place in accordance with the requirements `of the solution order, and being also tied up through the copying gates 57 and 53.

The registers 52 and 53 operate in sequence defining the strict order of stages.

In the initial condition of the circuit for counter 36 there is a fixed position corresponding to the first number of the factor, that on the register 44-t-o the second number of factor, on counter 51-to the third number of factor, while the registers are in zero condition. The pulses for rearranging equations are worked out in the chart of selecting root factors (inputs 59, 60 and 61).

On the first stage the pulse produced in the circuit of selecting root factors follows through the assembly 62 to the input of counter 36, increasing its contents by one unit. In this way, the counter 36 will show the next factor number, i.e. a new equation will be formed. On the first stage of the equation there will be one factor participating, on the second one-two different factors.

In order to distinguish the stages there is the register' 53 provided, which switches over the signals of the first or second stages. The counter 36 successively sorts out all the values and is thrown back into initial position, i.e. it tried out all the combinations from the z' elements one by one. The signal from the output of this counter appears on the input of the register 53 and transfers it into a unit condition. Then begins the second stage. In order to initially change the numbers of the second factor in the equation, as required by the algorithm, the signals of rearranging equations on the second stage follow through the assembly 63 to the input of counter 44, each time increasing its content by -one unit. Thus, the counter 44 will show after every rearranging, the next in order number of the factor. By gradually increasing the readings of counter 44, it will sort out all the values and will be thrown into zero condition, while the signal from its output will proceed to the input of counter 36, increasing its readings by one unit. By this the required order of numerical factor sequence will become disturbed: the numbers of the iirst factor on the counter 36 will show a larger number than the numbers of the second factor on the counter 44. In order to eliminate this discrepancy correction is provided in the circuit for composition equations, which is put into effe-ct by rewriting the adings of counter 36 to counter 44 and by adding to the mtent of the latter one more unit.

The pulse from the output of counter 44 proceeds to the :gister S4, transfers it into unit position and thereby yens up the gates 64 and 65. The rst synchronizing llse (which in the recording circuit registers the value in the summator) accomplishes through the gate 65 the :writing from the counter 36 to the counter 44 in direct 3de, and then, held up by the delay line 66, passes irough the gate 64, adding one unit to the counter 44 nd throwing into zero condition the register S4. Thus, efore starting the rewriting of this factor, the counter 4 fixes in the summator an lordinal number larger than iat on the counter 36 of the first factor, while the register 4 returned into zero position, ensures a one-time refriting and the addition of a unit.

On the third stage of the equation there already takes art three different factors. To determine the signal inication of the third stage the register 42 is used. As in he foregoing stages, the contents of counter 36 of the rst actor number again reaches the maximum value and yfter the signal of rearranging this counter, is also thrown nto initial position. The signal from the output of this `ounter follows through the open gate 67 to the output I6, through the gate 68 and to the register 512, bringing t into unit condition, thereby displaying the indication )f the third stage. In order, rst of all, to change in the vquation the numbers of the third factor, the signals of 'earranging (input 61) of equations follow through the tssembly 619 to the input of counter 51, each time increasng its content by one unit. The counter 51 sorts out all falues and is thrown into its initial condition, while its )utput pulse proceeds to the input of counter 44 increasf ng its readings by one unit. This will cause a disturbance )f the required order of sequence of the second and third factors, similar to the one that was described above. In arder to maintain the required order there is a correction Jrovided in the circuit, which is effected by re-writing the readings of counter 44 to counter 5l and by adding a .mit to the latter.

The gradually increasing readings of counter 44, second factor numbers, will cause disturbance of the sequence arder in the numbers of the first and second factors. But an the third stage this disturbance takes place simultaneous with that of the numbers of the second and third factors. For the successive correction of factor numbers the circuit is provided with a dependence allowing to transfer the readings from the counter 44 of the second factor number to the counter 51 of the third factor number only after corrections are made in the numbers of the first and second factors. This function is accomplished by the coincidence circuit 70 allowing the passing of the synchronizing pulses through the gates '71 and 72 and the delay line '73 for correcting the order of numbers of the second and third factors after completing the correcting of number orders of the first and second factors.

The recording circuit (FIG. 4) contains three decoders 74, 75 and 76 connected in parallel with the counters 36, 44 and 51 of the circuits for composing diophantine equations and through the gates '77, 78 and 79 with the summator controlled by this circuit, as well as the Iassembly 80 and the pulse shaper.

The counters of factor numbers define in the binary code the factor number, which should be recorded for the preset equation. The decoders convert the readings of the counters, i.e. a high level opening up of t-he gates appears on one of the bus-bars corresponding to the number xed on the counter. The recording pulses proceed to the gates from the circuit of selecting factor roots of equations (outputs 34, 43 and 45 of the circuit). In order to work out powerful pulses for copying the factors from the registers of initial data into the summator, there are the pulse shapers 81 with triple-input assemblies 80.

The herein described machine has two circuits for zero analysis. One circuit is designed for dening the zero value of the summator remnant; the other-tio dene the zero values of factor roots. Since all the factors from input registers of the machine are transmitted to the summator, the signal indication of zero factor is represented by the appearance of zero in ythe summator. Both circuits are similar in their construction, therefore, only one of them, for instance, the circuit defining the zero value of the summator remnant (FIG. 5), is Idescribed here.

The circuit consists of cascade multi-input coincidence charts 81-87. The inputs of the coincidence circuits are connected with the zero outputs of the summator and with those of the input registers. In this way, the high level signal appears on the output 88 of the circuit only, when high potentials characterizing the zero condition of the logical element of every category (for instance, the trigger) appear on the zero output of all categories of the summator.

Although this invention has been described in conformity with the preferred method of realization, it is to be understood, that changes and variations without deviating from the essence and scope of the invention, may take place. Such changes `and variations will be considered as not exceeding the scope of this invention when determined by the appended claims.

What we claim is:

1. An electronic computing machine for determining the optimum variant of cutting fabric into strips of a given length, comprising, in combination,

(a) a plurality of memory registers;

(b) means for inputting int-o said registers data relating to the total length of the fabric to be laid out, and data on the lengths of each of the strips required, with only one kind of data being introduced into each of the registers;

(c) summator means;

(d) means for connecting the outputs of said registers in parallel to the summator means;

(e) programmer means operatively connected to said registers and comprising:

(l) a first plurality of counters for the consecutive selection of combinations from the said registers and the transmission of the data from said registers to said summator means;

(2) a second plurality of counters connected to the input of the rst plurality, for setting the factors that characterize the number of times the data of each register is .to be introduced into said summator means, whereby the summator sums all the data received from the registers and is capable of producing one of `a signal of zero, when the capacity of the summator means coincides with the total sum of the data introduced into it, and a signal of overlling, when there is no coincidence;

(f) controllers connected to receive said signals of the summator means for terminating the calculations when a zero signal is sent, land for resetting said counters of the programmer means in order to set the next combination of registers to be used in the calculations and the values of the factors lapplied to the data introduced by the registers;

(g) registering devices connected to both groups of counters of the programmer means for indicating the registers to be used in each cycle of calcul-ations, the data contained in said registers and the factors to be used.

2. An electronic computing machine as claimed in claim 1, in which said first plurality of counters of the programmer means is connected i-n series, and further comprising means connected between adjacent counters for transfer- 3,319,055 9 10 ring the data from each successive Icounter to the previous References Cited by the Examiner counter `at the beginning of each cycle of the calculations, UNITED STATES PATENTS whereby new combinations of registers are selected which do not repeat the combinations used in the previous cal- 3,191,857 6/ 1965 Gale-y 234-3 culation cycle. 5 3,205,740 9/ 1965 Groves 8371 3. An electroni-c computing machine as claimed in claim FOREIGN PATENTS 1, further compnsmg means for consecutively changing the cap-acity of the summator means by an amount equal 795,284 6/1956 Great Entamto a unit of length in each calculation cycle, thereby ensuring a change in the length of remnant tolerated in cutting 0 MALCOLM A' MORRISON P' mary Exammer' a piece of fabric. K. MILDE, Assistant Examiner. 

1. AN ELECTRONIC COMPUTING MACHINE FOR DETERMINING THE OPTIMUM VARIANT OF CUTTING FABRIC INTO STRIPS OF A GIVEN LENGTH, COMPRISING, IN COMBINATION, (A) A PLURALITY OF MEMORY REGISTERS; (B) MEANS FOR INPUTTING INTO SAID REGISTERS DATA RELATING TO THE TOTAL LENGTH OF THE FABRIC TO BE LAID OUT, AND DATA ON THE LENGTHS OF EACH OF THE STRIPS REQUIRED, WITH ONLY ONE KIND OF A BEING INTRODUCED INTO EACH OF THE REGISTERS; (C) SUMMATOR MEANS; (D) MEANS FOR CONNECTING THE OUTPUTS OF SAID REGISTERS IN PARALLEL TO THE SUMMATOR MEANS; (E) PROGRAMMER MEANS OPERATIVELY CONNECTED TO SAID REGISTERS AND COMPRISING; (1) A FIRST PLURALITY OF COUNTERS FOR THE CONSECUTIVE SELECTION OF COMBINATION FROM THE SAID REGISTERS AND THE TRANSMISSION OF THE DATA FROM SAID REGISTERS TO SAID SUMMATOR MEANS; (2) A SECOND PLURALITY OF COUNTERS CONNECTED TO THE INPUT OF THE FIRST PLURALITY, FOR SETTLING THE FACTORS THAT CHARACTERIZED THE NUMBER OF TIMES THE DATA OF EACH REGISTER IS TO BE INTRODUCED INTO SAID SUMMATOR MEANS, WHEREBY THE SUMMATOR SUMS ALL THE DATA RECEIVED FROM THE REGISTERS AND IS CAPABLE OF PRODUCING ONE OF A SIGNAL OF ZERO, WHEN THE CAPACITY OF THE SUMMATOR MEANS COINCIDES WITH THE TOTAL SUM OF THE DATA INTRODUCED INTO IT, AND A SIGNAL OF OVERFILLING, WHEN THERE IS NO COINCIDENCE; (F) CONTROLLERS CONNECTED TO RECEIVE SAID SIGNALS OF THE SUMMATOR MEANS FOR TERMINATING THE CALCULATIONS WHEN A ZERO SIGNAL IS SENT, AND FOR RESETTING SAID COUNTERS OF THE PROGRAMMER MEANS IN ORDER TO SET THE NEXT COMBINATION OF REGISTERS TO BE USED IN THE CALCULATIONS AND THE VALUES OF THE FACTORS APPLIED TO THE DATA INTRODUCES BY THE REGISTERS; (G) REGISTERING DEVICES CONNECTED TO BOTH GROUPS OF COUNTERS OF THE PROGRAMMER MEANS FOR INDICATING THE REGISTERS TO BE USED IN EACH CYCLE OF CALCULATIONS, THE DATA CONTAINED IN SAID REGISTERS AND THE FACTORS TO BE USED. 